Skip to content
Home
About Us
Resources
Profiles Metrics
Authors Directory
Institutions Directory
Top Authors
Top Institutions
Top Sponsors
AI Digest
Contact Us
Menu
Home
About Us
Resources
Profiles Metrics
Authors Directory
Institutions Directory
Top Authors
Top Institutions
Top Sponsors
AI Digest
Contact Us
Home
About Us
Resources
Profiles Metrics
Authors Directory
Institutions Directory
Top Authors
Top Institutions
Top Sponsors
AI Digest
Contact Us
Menu
Home
About Us
Resources
Profiles Metrics
Authors Directory
Institutions Directory
Top Authors
Top Institutions
Top Sponsors
AI Digest
Contact Us
Publication Details
AFRICAN RESEARCH NEXUS
SHINING A SPOTLIGHT ON AFRICAN RESEARCH
computer science
A multi-FPGA architecture-based real-time TFM ultrasound imaging
Journal of Real-Time Image Processing, Volume 16, No. 2, Year 2019
Notification
URL copied to clipboard!
Description
Real-time imaging, using ultrasound techniques, is a complex task in non-destructive evaluation. In this context, fast and precise control systems require design of specialized parallel architectures. Total focusing method (TFM) for ultrasound imaging has many advantages in terms of flexibility and accuracy in comparison to traditional imaging techniques. However, one major drawback is the high number of data acquisitions and computing requirements for this imaging technique. Due to those constraints, the TFM algorithm was earlier classified in the field of post-processing tasks. This paper describes a multi-FPGA architecture for real-time TFM imaging using the full matrix capture (FMC). In the acquisition process, data are acquired using a phased array and processed with synthetic focusing techniques such as the TFM algorithm. The FMC-TFM architecture consists of a set of interconnected FPGAs integrated on an embedded system. Initially, this imaging system was dedicated to data acquisition using a phased array. The algorithm was reviewed and partitioned to parallelize processing tasks on FPGAs. The architecture was entirely described using VHDL language, synthesized and implemented on a V5FX70T Xilinx FPGA for the control and high-level processing tasks and four V5SX95T Xilinx FPGAs for the acquisition and low-level processing tasks. The designed architecture performs real-time FMC-TFM imaging with a good characterization of defects. © 2016, Springer-Verlag Berlin Heidelberg.
Authors & Co-Authors
El Ouardi, Abdelhafid E.
France, Palaiseau
Centre de Nanosciences et de Nanotechnologies
Bouaziz, Samir
France, Palaiseau
Centre de Nanosciences et de Nanotechnologies
Statistics
Citations: 24
Authors: 2
Affiliations: 2
Identifiers
Doi:
10.1007/s11554-016-0563-5
ISSN:
18618200