A new asynchronous pipeline scheme: Application to the design of a self-timed ring divider

This paper describes an efficient means of synchronizing and pipelining asynchronous circuits implemented using differential cascode voltage switch logic (DCVSL) [1] precharged function blocks. A modified version of this logic, called LDCVSL (latch differential cascode voltage switch logic), which is similar to the LCDL (latched CMOS differential logic [2]), or DCVSL with NORA-Latch [3], is used to improve the storage capability of the precharged function blocks. Improving the storage capability of the building blocks allows the design of an efficient pipeline scheme which is described in detail. Following a description of its potential performance, the pipeline scheme is applied to the design of self-timed rings. It is shown that more compact ring structures can be obtained without loss of performance. Our design methodology is then presented. It is based on the use of a private asynchronous standard cell library, fully compatible with an existing CMOS standard cell library provided by the foundry. Our approach allows the rapid design of standard cell based asynchronous circuits. Finally, both the pipeline scheme and design approach are illustrated through the design of a 32-b self-timed ring divider. The division algorithm is first briefly presented. The chip architecture is then described with the results obtained after fabrication. The test chip has been fabricated using the CNET/SGS-Thomson 0.5 μm three metal layer technology. The 0.7 mm2 chip computes 32-b divisions in 101 ns with a power consumption of 30 mW at a throughput of 10 million operations per second.